1. Field of the Invention
The present invention relates to a semiconductor device. More specifically, the invention relates to a method of laying out a semiconductor memory having hierarchized bit lines.
2. Description of the Related Art
In semiconductor memories, recently, the problem that leakage current from bit lines increases as a metal oxide semiconductor (hereinafter referred to as MOS) decreases in size has become serious. To solve this problem, the following measures have been taken. The bit lines are hierarchized and the number of memory cells electrically connected to one bit line is reduced to decrease leakage current of the bit lines (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 7-326186). If the bit lines are hierarchized, their capacities decrease and thus the memory access time is advantageously shortened.
If, however, the bit lines are hierarchized, a selection transfer gate is required to selectively connect the hierarchized bit lines to each other. This causes a problem that the reduction rate of the area of the entire layout will become lower than that of the area of MOS transistors.
There now follows a specific explanation of hierarchization of bit lines. The bit lines are usually formed throughout one column and hierarchized as a global bit line connected to a sense amplifier and a local bit line formed for each memory cell array. The global bit line and local bit line are connected to each other via a selection transfer gate that turns on in response to an address selection signal. The selection transfer gate is made up of a pair of MOS transistors (NMOS and PMOS switching transistors). The NMOS switching transistor is required to reliably apply a low potential (reference potential) to a memory cell when data is written to the memory cell. The PMOS switching transistor is required to sense a subtle variation in potential that is close to the power supply potential of the bit lines.
The global bit line and local bit line are formed of metal wiring layers of different levels. Usually, the global bit line is formed at a higher level than the local bit line. The interval between the global bit lines is very narrow in accordance with the size of each of memory cells, as is the interval between the local bit lines.
In the hierarchical bit-line architecture described above, the memory cells are formed in a memory cell array region on a semiconductor substrate. The PMOS and NMOS switching transistors of the selection transfer gate need to be formed in their respective N and P well regions on the semiconductor substrate. In order to electrically isolate the NMOS and PMOS switching transistors from each other, some distance is required from a boundary between the P and N well regions to the end of a MOS transistor formed on the P or N well region. This distance cannot be shortened so greatly, though the MOS transistors that make up a memory decrease in size year by year. Thus, the area of P and N well regions necessary for forming the NMOS and PMOS switching transistors becomes relatively large as the MOS transistors decrease in size. Consequently, the reduction rate of the area of the entire layout will become lower than that of the size of the MOS transistors.
If the NMOS and PMOS switching transistors are formed in different well regions, a P well region or an N well region is usually formed on one side of the memory cell array. In other words, one of the P and N well regions is located close to the memory cell array, while the other is located far from the memory cell array. The local bit line and global bit line are arranged in parallel above the MOS switching transistor located close to the memory cell array. The lower-level local bit line can be prevented from hindering a contact from being formed between the source/drain of the MOS switching transistor and the upper-level global bit line. In other words, the area of the entire layout will remarkably increase when it becomes necessary to increase an interval between the bit lines because of the contact.
As described above, the prior art semiconductor memory has the problem that the area of the entire layout is restricted by the area of the well region and the interval between the bit lines regardless of the reduction rate of the size of the MOS transistor.